Sciweavers

ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
13 years 9 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
13 years 9 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
13 years 10 months ago
A case for FAME: FPGA architecture model execution
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bi...
ISCA
2010
IEEE
314views Hardware» more  ISCA 2010»
13 years 10 months ago
Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis
Power consumption has become a major constraint in the design of processors today. To optimize a processor for energyefficiency requires an examination of energy-performance trade...
Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay...
ISCA
2010
IEEE
405views Hardware» more  ISCA 2010»
13 years 10 months ago
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU
Recent advances in computing have led to an explosion in the amount of data being generated. Processing the ever-growing data in a timely manner has made throughput computing an i...
Victor W. Lee, Changkyu Kim, Jatin Chhugani, Micha...
ISCA
2010
IEEE
284views Hardware» more  ISCA 2010»
13 years 10 months ago
Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address
Phase change memory (PCM) is an emerging memory technology for future computing systems. Compared to other non-volatile memory alternatives, PCM is more matured to production, and...
Nak Hee Seong, Dong Hyuk Woo, Hsien-Hsin S. Lee
ISCA
2010
IEEE
143views Hardware» more  ISCA 2010»
13 years 10 months ago
Web search using mobile cores: quantifying and mitigating the price of efficiency
Vijay Janapa Reddi, Benjamin C. Lee, Trishul M. Ch...
ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
13 years 10 months ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron
ISCA
2010
IEEE
236views Hardware» more  ISCA 2010»
13 years 10 months ago
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
Enric Herrero, José González, Ramon ...
ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
13 years 10 months ago
Data marshaling for multi-core architectures
Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to bes...
M. Aater Suleman, Onur Mutlu, José A. Joao,...