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ISCAS
1999
IEEE
74views Hardware» more  ISCAS 1999»
9 years 1 months ago
A low-power switched-current algorithmic A/D converter
This paper reports the development of a low-power switchedcurrent algorithmic A/D converter based on a new algorithm, providing the bit conversion in three-cycles. The converter u...
A. Tezel, T. Akin
ISCAS
1999
IEEE
77views Hardware» more  ISCAS 1999»
9 years 1 months ago
Power reduction through iterative gate sizing and voltage scaling
The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-...
Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, W...
ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
9 years 1 months ago
A low power scheduling scheme with resources operating at multiple voltages
This paper presents resource and latency constrained scheduling algorithms to minimize power/energy consumption when the resources operate at multiple voltages (5 V, 3.3 V,
Ali Manzak, Chaitali Chakrabarti
ISCAS
1999
IEEE
102views Hardware» more  ISCAS 1999»
9 years 1 months ago
Power and signal integrity improvement in ultra high-speed current mode logic
Current mode (ECL) logic has long been the option of choice in those applications requiring logic functions at multigigahertz rates. This trend continues despite the obvious very ...
Hien Ha, Forrest Brewer
ISCAS
1999
IEEE
114views Hardware» more  ISCAS 1999»
9 years 1 months ago
Channel equalization by feedforward neural networks
A signal su ers from nonlinear, linear, and additive distortion when transmitted through a channel. Linear equalizers are commonly used in receivers to compensate for linear chann...
Biao Lu, Brian L. Evans
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