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ISCAS
1999
IEEE

CMOS gate modeling based on equivalent inverter

9 years 2 months ago
CMOS gate modeling based on equivalent inverter
A method for modeling complex CMOS gates by the reduction of each gate to an effective equivalent inverter is introduced. The conducting and parasitic behavior of parallel and serially connected transistors is accurately analyzed and an equivalent transistor is extracted for each case, taking into account the actual operating conditions of each device in the structure. The accuracy of the method is validated by the results for two submicron technologies and its efficiency as a technique that can improve existing timing simulators is demonstrated.
Alexander Chatzigeorgiou, Spiridon Nikolaidis, Ioa
Added 04 Aug 2010
Updated 04 Aug 2010
Type Conference
Year 1999
Where ISCAS
Authors Alexander Chatzigeorgiou, Spiridon Nikolaidis, Ioannis Tsoukalas, Odysseas G. Koufopavlou
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