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ISCAS
2006
IEEE
128views Hardware» more  ISCAS 2006»
13 years 10 months ago
Modeling and verification of high-speed wired links with Verilog-AMS
—Behavioral modeling with virtual built-in self-test verification of high-speed wired link designs is described in this paper. Our procedure is based on principles of top-down mi...
Ming-Ta Hsieh, Gerald E. Sobelman
ISCAS
2006
IEEE
65views Hardware» more  ISCAS 2006»
13 years 10 months ago
Symbolic analysis of bifurcations in planar variable structure systems
— In this paper a methodology to the analysis of bifurcations of variable structure systems is proposed. This methodology, based on the use of symbolic computation packages, is d...
Ubirajara F. Moreno, Eugênio B. Castelan, Ed...
ISCAS
2006
IEEE
92views Hardware» more  ISCAS 2006»
13 years 10 months ago
Time-sliding suboptimal regulation of bilinear interconnected systems
— This paper focuses on the suboptimal regulation of multivariable discrete-time bilinear systems consisting of interconnected bilinear subsystems with respect to a linear quadra...
Manuel de la Sen, Aitor J. Garrido, J. C. Soto, Os...
ISCAS
2006
IEEE
93views Hardware» more  ISCAS 2006»
13 years 10 months ago
Discontinuity-induced bifurcations in TCP/RED communication algorithms
— In this paper, we describe a simple second-order discrete-time model for the Transmission Control Protocol (TCP) with Random Early Detection (RED) algorithm. The TCP/RED mechan...
Mingjian Liu, A. Marciello, Mario di Bernardo, Lji...
ISCAS
2006
IEEE
96views Hardware» more  ISCAS 2006»
13 years 10 months ago
In-scale motion aligned temporal filtering
— To handle the mismatch problems of spatial-domain motion aligned temporal filtering (MATF) in providing spatial scalability, this paper presents a novel in-scale motion aligne...
Ruiqin Xiong, Jizheng Xu, Feng Wu, Shipeng Li
ISCAS
2006
IEEE
101views Hardware» more  ISCAS 2006»
13 years 10 months ago
A cost-effective reconfigurable accelerator for platform-based SOC design
In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-on-a-chip (SoC) design. Based on the proposed design methodology, the reconfigu...
Lan-Da Van, Hsin-Fu Luo, Nien-Hsiang Chang, Chun-M...
ISCAS
2006
IEEE
81views Hardware» more  ISCAS 2006»
13 years 10 months ago
Fully programmable bias current generator with 24 bit resolution per bias
This paper describes an on-chip programmable bias current generator, intended for mixed signal chips requiring a wide ranging set of currents. The individual generators share a ma...
Tobi Delbrück, Patrick Lichtsteiner
ISCAS
2006
IEEE
150views Hardware» more  ISCAS 2006»
13 years 10 months ago
A character size optimization technique for throughput enhancement of character projection lithography
— We propose a character size optimization technique to enhance the throughput of maskless lithography as well as photomask manufacture. The number of electron beam shots to draw...
Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryo...
ISCAS
2006
IEEE
107views Hardware» more  ISCAS 2006»
13 years 10 months ago
Design and implementation of content-adaptive background skipping for wireless video
—This work presents a low-complexity system implementation of a novel content-adaptive background skipping scheme for region-of-interest (ROI) video coding in mobile video phone ...
Yi Liang, Haohong Wang, Khaled El-Maleh
ISCAS
2006
IEEE
127views Hardware» more  ISCAS 2006»
13 years 10 months ago
Constant transconductance bias circuit with an on-chip resistor
A method to generate stable transconductance (gm) without using precise external components is presented. The off-chip resistor in a conventional constant-gm bias circuit is repla...
N. Talebbeydokhti, Pavan Kumar Hanumolu, P. Kuraha...