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ISCAS
2006
IEEE
79views Hardware» more  ISCAS 2006»
13 years 11 months ago
A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application
—In this paper, we propose a cost-effective and low-power 64-point fast Fourier transform (FFT)/inverse FFT (IFFT) architecture and chip adopting the retrenched 8-point FFT/IFFT ...
Chin-Teng Lin, Yuan-Chu Yu, Lan-Da Van
ISCAS
2006
IEEE
118views Hardware» more  ISCAS 2006»
13 years 11 months ago
Complex network topologies and synchronization
Synchronization in networks with different topolo- is shown that for typical systems only three main scenarios gies is studied. We show that for a large class of oscillators there ...
Paolo Checco, Mario Biey, Gábor Vattay, Lju...
ISCAS
2006
IEEE
108views Hardware» more  ISCAS 2006»
13 years 11 months ago
A low complexity hardware architecture for motion estimation
This paper tackles the problem of accelerating The rest of this paper is organised as follows: section II motion estimation for video processing. A novel architecture details relat...
Daniel Larkin, Vlenti. Muresan, Noel E. O'Connor
ISCAS
2006
IEEE
135views Hardware» more  ISCAS 2006»
13 years 11 months ago
Image compression with structure-aware inpainting
— This paper carves out a way to image compression that is motivated by the recent advancement in image inpainting. An image coding approach is proposed in which a number of regi...
Chen Wang, Xiaoyan Sun, Feng Wu, Hongkai Xiong
ISCAS
2006
IEEE
68views Hardware» more  ISCAS 2006»
13 years 11 months ago
Real-time seizure monitoring and spectral analysis microsystem
We present a neural recording and spectral analysis RECORDING ANALYSIS integrated microsystem. It is the instrumentational and computa- INTERACE PROCESSOR tional core of an envisio...
J. N. Y. Aziz, Rafal Karakiewicz, Roman Genov, B. ...
ISCAS
2006
IEEE
103views Hardware» more  ISCAS 2006»
13 years 11 months ago
A low-power geometric mapping co-processor for high-speed graphics application
Abstract— In this article we present a novel design of a lowpower geometric mapping co-processor that can be used for high-performance graphics system. The processor can carry ou...
S. Leeke, L. Maharatna
ISCAS
2006
IEEE
77views Hardware» more  ISCAS 2006»
13 years 11 months ago
A parallel search algorithm for CLNS addition optimization
— We present analytical formulas for the calculation of the memory requirements for a system using the Complex Logarithmic Number System (CLNS). Certain properties of the CLNS ad...
Panagiotis D. Vouzis, Mark G. Arnold
ISCAS
2006
IEEE
80views Hardware» more  ISCAS 2006»
13 years 11 months ago
Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter
We examine noise due to clock jitter in single-loop low pass continuous-time delta-sigma modulators employing NRZ feedback DACs. Using the discrete-time version of the Bode sensit...
K. Reddy, S. Pavan
ISCAS
2006
IEEE
205views Hardware» more  ISCAS 2006»
13 years 11 months ago
A CMOS integrated linear voltage-to-pulse-delay-time converter for time based analog-to-digital converters
A novel 0. 13,um CMOS integrated linear voltage to pulse delay time converter (VTC) is proposed. The VTC ml architecture uses current starved inverters where the inverter delay ver...
Holly Pekau, A. Yousif, James W. Haslett
ISCAS
2006
IEEE
132views Hardware» more  ISCAS 2006»
13 years 11 months ago
CMOS voltage-mode analog multiplier
Boonchai Boonchu, Wanlop Surakampontorn