Sciweavers

ISCAS
2006
IEEE
79views Hardware» more  ISCAS 2006»
13 years 10 months ago
Chip-scale magnetic sensing and control of nanoparticles and nanorods
— We report on a system designed for the magnetic control of nanoparticles and nanorods. This is accomplished by arrays of current-carrying wires (electromagnets) and the associa...
Edward Choi, Zhiyong Gu, D. Gracias, Andreas G. An...
ISCAS
2006
IEEE
77views Hardware» more  ISCAS 2006»
13 years 10 months ago
Modeling orientation selectivity using a neuromorphic multi-chip system
Elisabetta Chicca, Patrick Lichtsteiner, Tobi Delb...
ISCAS
2006
IEEE
108views Hardware» more  ISCAS 2006»
13 years 10 months ago
Design methodology for global resonant H-tree clock distribution networks
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
Jonathan Rosenfeld, Eby G. Friedman
ISCAS
2006
IEEE
106views Hardware» more  ISCAS 2006»
13 years 10 months ago
Integrating observability don't cares in all-solution SAT solvers
— All-solution Boolean satisfiability (SAT) solvers are engines employed to find all the possible solutions to a SAT problem. Their applications are found throughout the EDA in...
Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
ISCAS
2006
IEEE
70views Hardware» more  ISCAS 2006»
13 years 10 months ago
A portable all-digital pulsewidth control loop for SOC applications
—A cell-based all-digital PWCL is presented in this paper. To improve design effort as well as facilitate systemlevel integration, the new design can be developed in hardware des...
Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu
ISCAS
2006
IEEE
88views Hardware» more  ISCAS 2006»
13 years 10 months ago
An aVLSI recurrent network of spiking neurons with reconfigurable and plastic synapses
Davide Badoni, Massimiliano Giulioni, Vittorio Dan...
ISCAS
2006
IEEE
95views Hardware» more  ISCAS 2006»
13 years 10 months ago
Vertex cache of programmable geometry processor for mobile multimedia application
Vertex cache of programmable geometry processor The proposed architecture of vertex cache is divided into is proposed and implemented. The proposed vertex cache is pre-TnL vertex c...
Kyusik Chung, Chang-Hyo Yu, Lee-Sup Kim
ISCAS
2006
IEEE
90views Hardware» more  ISCAS 2006»
13 years 10 months ago
A novel ternary more, less and equality circuit using recharged semi-floating gate devices
— This paper presents a novel Ternary More, Less and Equality (MLE) Circuit implemented with Recharged SemiFloating Gate Transistors. The circuit is a ternary application, and te...
Henning Gundersen, Yngvar Berg
ISCAS
2006
IEEE
92views Hardware» more  ISCAS 2006»
13 years 10 months ago
The optimal MAC layer for low-power UWB is non-coordinated
— We consider the design of the MAC layer for low power, low data-rate, impulse-radio ultra-wide band (IRUWB) networks. In such networks, the primary concern is energy consumptio...
Ruben Merz, Alaeddine El Fawal, Jean-Yves Le Boude...
ISCAS
2006
IEEE
109views Hardware» more  ISCAS 2006»
13 years 10 months ago
Network-on-chip quality-of-service through multiprotocol label switching
Abstract— Providing Quality-of-Service (QoS) in networks-onchip (NoCs) will be an important consideration for the complex multiprocessor chips of the future. In this paper, we di...
Manho Kim, Daewook Kim, Gerald E. Sobelman