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ISCAS
2007
IEEE
105views Hardware» more  ISCAS 2007»
13 years 11 months ago
Parallel current-steering D/A Converters for Flexibility and Smartness
—This paper presents a DAC architecture built on parallel current-steering sub-DAC entities. Two main novelties are explored: flexibility and smartness. Firstly, a number of avai...
Georgi I. Radulov, Patrick J. Quinn, Pieter Harpe,...
ISCAS
2007
IEEE
133views Hardware» more  ISCAS 2007»
13 years 11 months ago
Volterra Analysis Using Chebyshev Series
— The paper presents a new approach to the Volterra analysis of analog circuits. This kind of analysis is widely used for the calculation of distortion and intermodulation produc...
Ioannis Sarkas, Dimitrios Mavridis, Michail Papami...
ISCAS
2007
IEEE
106views Hardware» more  ISCAS 2007»
13 years 11 months ago
Regularized Frequency Domain Equalization Algorithm and its VLSI Implementation
Abstract— Approximation of Toeplitz matrices with circulant matrices is a well-known approach to reduce the computational complexity of linear equalizers. This paper presents a n...
Andreas Burg, Simon Haene, Wolfgang Fichtner, Mark...
ISCAS
2007
IEEE
133views Hardware» more  ISCAS 2007»
13 years 11 months ago
Design of a Massively Parallel Vision Processor based on Multi-SIMD Architecture
— Increasing demands for robust image recognition systems require vision processors not only with enormous computational capacities but also with sufficient flexibility to hand...
Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro...
ISCAS
2007
IEEE
124views Hardware» more  ISCAS 2007»
13 years 11 months ago
CMOS Current-controlled Oscillators
— The work presented in this paper is about the design of current-controlled oscillators (ICO). Two ICOs are proposed. Aiming at reducing the duration of the short-circuit curren...
Junhong Zhao, Chunyan Wang
ISCAS
2007
IEEE
120views Hardware» more  ISCAS 2007»
13 years 11 months ago
Clock Gating and Negative Edge Triggering for Energy Recovery Clock
Energy recovery clocking has been demonstrated as an effective method for reducing the clock power. In this method the conventional square wave clock signal is replaced by a sinus...
Vishwanadh Tirumalashetty, Hamid Mahmoodi
ISCAS
2007
IEEE
112views Hardware» more  ISCAS 2007»
13 years 11 months ago
Motion Mapping for MPEG-2 to H.264/AVC Transcoding
This paper describes novel motion mapping algorithms aimed for low-complexity MPEG-2 to AVC transcoding. The proposed algorithms efficiently map incoming MPEG-2 motion vectors to...
Jun Xin, Jianjun Li, Anthony Vetro, Huifang Sun, S...
ISCAS
2007
IEEE
84views Hardware» more  ISCAS 2007»
13 years 11 months ago
High Speed 1-bit Bypass Adder Design for Low Precision Additions
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
Jong-Suk Lee, Dong Sam Ha
ISCAS
2007
IEEE
84views Hardware» more  ISCAS 2007»
13 years 11 months ago
A Pipelined A/D Conversion Technique with Low INL and DNL
Jingbo Duan, Fule Li, Liyuan Liu, Dongmei Li, Yong...
ISCAS
2007
IEEE
112views Hardware» more  ISCAS 2007»
13 years 11 months ago
A New Statistical Approach for Glitch Estimation in Combinational Circuits
— Low-power consumption has become a highly important concern for synchronous standard-cell design, and consequently mandates the use of low-power design methodologies and techni...
Ahmed Sayed, Hussain Al-Asaad