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ISLPED
2003
ACM
197views Hardware» more  ISLPED 2003»
13 years 9 months ago
Analyzing the energy consumption of security protocols
Security is critical to a wide range of wireless data applications and services. While several security mechanisms and protocols have been developed in the context of the wired In...
Nachiketh R. Potlapally, Srivaths Ravi, Anand Ragh...
ISLPED
2003
ACM
95views Hardware» more  ISLPED 2003»
13 years 9 months ago
Power efficient comparators for long arguments in superscalar processors
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad ...
ISLPED
2003
ACM
88views Hardware» more  ISLPED 2003»
13 years 9 months ago
Reducing data cache energy consumption via cached load/store queue
High-performance processors use a large set–associative L1 data cache with multiple ports. As clock speeds and size increase such a cache consumes a significant percentage of t...
Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru...
ISLPED
2003
ACM
142views Hardware» more  ISLPED 2003»
13 years 9 months ago
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization
We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous a...
David Nguyen, Abhijit Davare, Michael Orshansky, D...
ISLPED
2003
ACM
77views Hardware» more  ISLPED 2003»
13 years 9 months ago
Microprocessor pipeline energy analysis
The increase in high-performance microprocessor power consumption is due in part to the large power overhead of wideissue, highly speculative cores. Microarchitectural speculation...
Karthik Natarajan, Heather Hanson, Stephen W. Keck...
ISLPED
2003
ACM
100views Hardware» more  ISLPED 2003»
13 years 9 months ago
Checkpointing alternatives for high performance, power-aware processors
High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes u...
Andreas Moshovos
ISLPED
2003
ACM
82views Hardware» more  ISLPED 2003»
13 years 9 months ago
Multivoltage scheduling with voltage-partitioned variable storage
Multivoltage scheduling (MVS) for datapaths offers the energy savings of voltage scaling on a per-operation basis with a voltage aware operator scheduling. This work investigates...
Amitabh Menon, S. K. Nandy, Mahesh Mehendale
ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
13 years 9 months ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
ISLPED
2003
ACM
91views Hardware» more  ISLPED 2003»
13 years 9 months ago
Reducing reorder buffer complexity through selective operand caching
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad ...
ISLPED
2003
ACM
94views Hardware» more  ISLPED 2003»
13 years 9 months ago
Evolution of low power electronics and its future applications
Low power technology is impacting our society by creating the newly emerging digital consumer market, which leads to the nomadic life-style. In this paper, historical review of th...
Tsugio Makimoto, Yoshio Sakai