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ISLPED
2005
ACM
88views Hardware» more  ISLPED 2005»
13 years 10 months ago
PARE: a power-aware hardware data prefetching engine
Aggressive hardware prefetching often significantly increases energy consumption in the memory system. Experiments show that a major fraction of prefetching related energy degrad...
Yao Guo, Mahmoud Ben Naser, Csaba Andras Moritz
ISLPED
2005
ACM
119views Hardware» more  ISLPED 2005»
13 years 10 months ago
FinFET-based SRAM design
Intrinsic variations and challenging leakage control in today’s bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRA...
Zheng Guo, Sriram Balasubramanian, Radu Zlatanovic...
ISLPED
2005
ACM
136views Hardware» more  ISLPED 2005»
13 years 10 months ago
Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy
Concerns about the reliability of real-time embedded systems that employ dynamic voltage scaling has recently been highlighted [1,2,3], focusing on transient-fault-tolerance techn...
Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Ha...
ISLPED
2005
ACM
109views Hardware» more  ISLPED 2005»
13 years 10 months ago
Power reduction by varying sampling rate
The rate at which a digital signal processing (DSP) system operates depends on the highest frequency component in the input signal. DSP applications must sample their inputs at a ...
William R. Dieter, Srabosti Datta, Wong Key Kai
ISLPED
2005
ACM
87views Hardware» more  ISLPED 2005»
13 years 10 months ago
Runtime identification of microprocessor energy saving opportunities
High power consumption and low energy efficiency have become significant impediments to future performance improvements in modern microprocessors. This paper contributes to the so...
W. L. Bircher, M. Valluri, J. Law, L. K. John
ISLPED
2005
ACM
101views Hardware» more  ISLPED 2005»
13 years 10 months ago
Energy-aware fetch mechanism: trace cache and BTB customization
1 A highly-efficient fetch unit is essential not only to obtain good performance but also to achieve energy efficiency. However, existing designs are inflexible and depending on pr...
Daniel Chaver, Miguel A. Rojas, Luis Piñuel...
ISLPED
2005
ACM
96views Hardware» more  ISLPED 2005»
13 years 10 months ago
Power-optimal repeater insertion considering Vdd and Vth as design freedoms
This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion ...
Yu Ching Chang, King Ho Tam, Lei He
ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
13 years 10 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
ISLPED
2005
ACM
98views Hardware» more  ISLPED 2005»
13 years 10 months ago
Synonymous address compaction for energy reduction in data TLB
Modern processors can issue and execute multiple instructions per cycle, often performing multiple memory operations simultaneously. To reduce stalls due to resource conflicts, m...
Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, M...
ISLPED
2005
ACM
102views Hardware» more  ISLPED 2005»
13 years 10 months ago
Snug set-associative caches: reducing leakage power while improving performance
As transistors keep shrinking and on-chip data caches keep growing, static power dissipation due to leakage of caches takes an increasing fraction of total power in processors. Se...
Jia-Jhe Li, Yuan-Shin Hwang