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ISLPED
2005
ACM
84views Hardware» more  ISLPED 2005»
13 years 10 months ago
Hierarchical power management with application to scheduling
This paper presented a hierarchical power management architecture which aims to facilitate power-awareness in an Energy-Managed Computer (EMC) system with multiple components. The...
Peng Rong, Massoud Pedram
ISLPED
2005
ACM
147views Hardware» more  ISLPED 2005»
13 years 10 months ago
System level power and performance modeling of GALS point-to-point communication interfaces
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
Koushik Niyogi, Diana Marculescu
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
13 years 10 months ago
Peak temperature control and leakage reduction during binding in high level synthesis
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
13 years 10 months ago
Energy reduction in multiprocessor systems using transactional memory
The emphasis in microprocessor design has shifted from high performance, to a combination of high performance and low power. Until recently, this trend was mostly true for uniproc...
Tali Moreshet, R. Iris Bahar, Maurice Herlihy
ISLPED
2005
ACM
72views Hardware» more  ISLPED 2005»
13 years 10 months ago
A low power current steering digital to analog converter in 0.18 Micron CMOS
This paper discusses a number of circuit techniques which address the DC and AC distortion performance of a low power current steering Digital-to-Analog Converter design. The desi...
Douglas Mercer
ISLPED
2005
ACM
90views Hardware» more  ISLPED 2005»
13 years 10 months ago
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
Yingmin Li, Mark Hempstead, Patrick Mauro, David B...
ISLPED
2005
ACM
110views Hardware» more  ISLPED 2005»
13 years 10 months ago
Complexity reduction in an nRERL microprocessor
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
Seokkee Kim, Soo-Ik Chae
ISLPED
2005
ACM
68views Hardware» more  ISLPED 2005»
13 years 10 months ago
Two efficient methods to reduce power and testing time
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
Il-soo Lee, Tony Ambler
ISLPED
2005
ACM
98views Hardware» more  ISLPED 2005»
13 years 10 months ago
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage
Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean...
ISLPED
2005
ACM
122views Hardware» more  ISLPED 2005»
13 years 10 months ago
A simple mechanism to adapt leakage-control policies to temperature
Leakage power reduction in cache memories continues to be a critical area of research because of the promise of a significant pay-off. Various techniques have been developed so fa...
Stefanos Kaxiras, Polychronis Xekalakis, Georgios ...