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ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
13 years 8 months ago
Low Power Storage Cycle Budget Distribution Tool Support for Hierarchical Graphs
In data dominated applications, like multi-media and telecom applications, data storage and transfers are the most important factors in terms of energy consumption, area and syste...
Erik Brockmeyer, Arnout Vandecappelle, Sven Wuytac...
ISSS
2000
IEEE
109views Hardware» more  ISSS 2000»
13 years 8 months ago
FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors
The paper presents a novel software-pipelining algorithm suitable for optimizing compilers targeting embedded VLIW processors. The proposed algorithm is different from previous ap...
Cagdas Akturan, Margarida F. Jacome
ISSS
2000
IEEE
191views Hardware» more  ISSS 2000»
13 years 8 months ago
Conditional Scheduling for Embedded Systems using Genetic List Scheduling
One important part of a HW/SW codesign system is the scheduler which is needed in order to determine if a given HW/SW partitioning is suitable for a given application. In this pap...
Martin Grajcar
ISSS
2000
IEEE
155views Hardware» more  ISSS 2000»
13 years 9 months ago
Intervals in Software Execution Cost Analysis
Timing and power consumption of embedded systems are state and input data dependent. Formal analysis of such dependencies leads to intervals rather than single values. These inter...
Fabian Wolf, Rolf Ernst
ISSS
2000
IEEE
123views Hardware» more  ISSS 2000»
13 years 9 months ago
Source Code Optimization and Profiling of Energy Consumption in Embedded Systems
Tajana Simunic, Giovanni De Micheli, Luca Benini, ...
ISSS
2000
IEEE
129views Hardware» more  ISSS 2000»
13 years 9 months ago
IP Reuse in the System on a Chip Era
Intellectual Property (IP) Reuse is one of the keys for System on a Chip (SoC) design productivity improvement. Although IP reuse has been explored both technically and as a busin...
Warren Savage, John Chilton, Raul Camposano
14
Voted
ISSS
2000
IEEE
128views Hardware» more  ISSS 2000»
13 years 9 months ago
Hardware Synthesis from SPDF Representation for Multimedia Applications
Even though high-level hardware synthesis from dataflow graphs becomes popular in designing DSP systems, currently used dataflow models are inefficient to deal with emerging multi...
Chanik Park, Soonhoi Ha
ISSS
2000
IEEE
91views Hardware» more  ISSS 2000»
13 years 9 months ago
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
Tony Givargis, Frank Vahid, Jörg Henkel
ISSS
2000
IEEE
88views Hardware» more  ISSS 2000»
13 years 9 months ago
Experiments with the Peripheral Virtual Component Interface
The Peripheral Virtual Component Interface, or PVCI, is a standard intended to simplify the interfacing of peripheral cores to on-chip buses in a system-on-a-chip, by standardizin...
Roman L. Lysecky, Frank Vahid, Tony Givargis