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PACS
2000
Springer
132views Hardware» more  PACS 2000»
9 years 7 months ago
An Adaptive Issue Queue for Reduced Power at High Performance
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue ...
Alper Buyuktosunoglu, Stanley Schuster, David Broo...
CF
2007
ACM
9 years 7 months ago
By-passing the out-of-order execution pipeline to increase energy-efficiency
Out-of-order execution significantly increases the performance of superscalar processors. The out-of-order execution mechanism is, however, energy-inefficient, which inhibits scal...
Hans Vandierendonck, Philippe Manet, Thibault Dela...
ISCA
2002
IEEE
80views Hardware» more  ISCA 2002»
9 years 8 months ago
A Large, Fast Instruction Window for Tolerating Cache Misses
Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instructi...
Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson K...
HIPC
2003
Springer
9 years 8 months ago
Power-Aware Adaptive Issue Queue and Register File
In this paper, we present a novel technique to reduce dynamic and static power dissipation in the issue queue. The proposed scheme is based on delaying the dispatch of instructions...
Jaume Abella, Antonio González
MICRO
2003
IEEE
108views Hardware» more  MICRO 2003»
9 years 9 months ago
Reducing Design Complexity of the Load/Store Queue
With faster CPU clocks and wider pipelines, all relevant microarchitecture components should scale accordingly. There have been many proposals for scaling the issue queue, registe...
Il Park, Chong-liang Ooi, T. N. Vijaykumar
PACS
2004
Springer
115views Hardware» more  PACS 2004»
9 years 9 months ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...
ICS
2005
Tsinghua U.
9 years 9 months ago
Low-power, low-complexity instruction issue using compiler assistance
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
Madhavi Gopal Valluri, Lizy Kurian John, Kathryn S...
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
9 years 9 months ago
Instruction packing: reducing power and delay of the dynamic scheduling logic
The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for...
Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghos...
HIPEAC
2007
Springer
9 years 9 months ago
Fetch Gating Control Through Speculative Instruction Window Weighting
In a dynamic reordering superscalar processor, the front-end fetches instructions and places them in the issue queue. Instructions are then issued by the back-end execution core. T...
Hans Vandierendonck, André Seznec
DSN
2008
IEEE
9 years 10 months ago
Analysis and solutions to issue queue process variation
The last few years have witnessed an unprecedented explosion in transistor densities. Diminutive feature sizes have enabled microprocessor designers to break the billion-transisto...
Niranjan Soundararajan, Aditya Yanamandra, Chrysos...
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