PACS
2000
Springer
13 years 8 months ago
2000
Springer
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue ...
CF
2007
ACM
13 years 9 months ago
2007
ACM
Out-of-order execution significantly increases the performance of superscalar processors. The out-of-order execution mechanism is, however, energy-inefficient, which inhibits scal...
ISCA
2002
IEEE
13 years 10 months ago
2002
IEEE
Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instructi...
HIPC
2003
Springer
13 years 10 months ago
2003
Springer
In this paper, we present a novel technique to reduce dynamic and static power dissipation in the issue queue. The proposed scheme is based on delaying the dispatch of instructions...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
With faster CPU clocks and wider pipelines, all relevant microarchitecture components should scale accordingly. There have been many proposals for scaling the issue queue, registe...
PACS
2004
Springer
13 years 10 months ago
2004
Springer
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
ICS
2005
Tsinghua U.
13 years 10 months ago
2005
Tsinghua U.
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for...
HIPEAC
2007
Springer
13 years 11 months ago
2007
Springer
In a dynamic reordering superscalar processor, the front-end fetches instructions and places them in the issue queue. Instructions are then issued by the back-end execution core. T...
DSN
2008
IEEE
13 years 11 months ago
2008
IEEE
The last few years have witnessed an unprecedented explosion in transistor densities. Diminutive feature sizes have enabled microprocessor designers to break the billion-transisto...