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ISVLSI
2003
IEEE
103views VLSI» more  ISVLSI 2003»
9 years 6 months ago
Energy Recovering ASIC Design
Abstract— Dissipation in the clock tree and state elements of ASIC designs is often a significant fraction of total energy consumption. We propose a methodology for recovering m...
Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthy...
ISVLSI
2003
IEEE
101views VLSI» more  ISVLSI 2003»
9 years 6 months ago
Energy Benefits of a Configurable Line Size Cache for Embedded Systems
Previous work has shown that cache line sizes impact performance differently for different desktop programs – some programs work better with small line sizes, others with larger...
Chuanjun Zhang, Frank Vahid, Walid A. Najjar
ISVLSI
2003
IEEE
115views VLSI» more  ISVLSI 2003»
9 years 6 months ago
Equalizing Filter Design for Crosstalk Cancellation
Jihong Ren, Mark R. Greenstreet
ISVLSI
2003
IEEE
93views VLSI» more  ISVLSI 2003»
9 years 6 months ago
Peak Power Minimization Through Datapath Scheduling
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
ISVLSI
2003
IEEE
157views VLSI» more  ISVLSI 2003»
9 years 6 months ago
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
Shalini Ghosh, Sugato Basu, Nur A. Touba
ISVLSI
2003
IEEE
118views VLSI» more  ISVLSI 2003»
9 years 6 months ago
Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication
In this paper, we discuss the possibility of achieving onchip fault-tolerant communication based on a new communication paradigm called stochastic communication. Specifically, for...
Radu Marculescu
ISVLSI
2003
IEEE
138views VLSI» more  ISVLSI 2003»
9 years 6 months ago
Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory
The need for small, high speed, low power computers as the end of Moore’s law approaches is driving research into nanotechnology. These novel devices have significantly differe...
Sarah E. Frost, Arun Rodrigues, Charles A. Giefer,...
ISVLSI
2003
IEEE
115views VLSI» more  ISVLSI 2003»
9 years 6 months ago
Getting High-Performance Silicon from System-Level Design
System-level design techniques promise a way to lessen the productivity gap between fabrication and design. Unfortunately, these techniques have been slow to catch on, in part bec...
W. Rhett Davis
ISVLSI
2003
IEEE
91views VLSI» more  ISVLSI 2003»
9 years 6 months ago
Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools
Three-dimensional integration technologies have been proposed in order to mitigate design challenges posed by deep-submicron interconnect. By providing multiple layers of active d...
Shamik Das, Anantha Chandrakasan, Rafael Reif
ISVLSI
2003
IEEE
99views VLSI» more  ISVLSI 2003»
9 years 6 months ago
Fast and Precise Power Prediction for Combinational Circuits
Hongping Li, John K. Antonio, Sudarshan K. Dhall
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