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ISVLSI
2003
IEEE

Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools

9 years 6 months ago
Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools
Three-dimensional integration technologies have been proposed in order to mitigate design challenges posed by deep-submicron interconnect. By providing multiple layers of active devices together with high-density local interconnects between these layers, 3-D technologies give digitalcircuit designers greater freedom in meeting power and delay budgets that are increasingly interconnect-dominated. In this paper, we quantify the benefits 3-D integration can provide, using specific circuit benchmarks. We perform this analysis using a suite of circuit design tools we have developed for 3-D integration. We observe that on average, 28% to 51% reduction in total wire length is possible over two to five wafers respectively; similarly, 31% to 56% reduction in the length of the longest wire is achievable. We also characterize the impact of technology parameters on these reductions.
Shamik Das, Anantha Chandrakasan, Rafael Reif
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ISVLSI
Authors Shamik Das, Anantha Chandrakasan, Rafael Reif
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