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ISVLSI
2003
IEEE

Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering

9 years 6 months ago
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random ordering of the scan cells. For a given test set, our proposed greedy algorithm finds the (locally) optimal scan cell ordering for a given value of λ, which is a trade-off parameter that can be used by the designer to specify the relative importance of area overhead minimization and power minimization. The strength of our algorithm lies in the fact that we use a novel dynamic minimum transition fill (MT-fill) technique to fill the unspecified bits in the test vector. Experiments performed on the ISCAS-89 benchmark suite show a reduction in power (70% for s13207, λ = 500) as well as a reduction in layout area (6.72% for s13207, λ = 500).
Shalini Ghosh, Sugato Basu, Nur A. Touba
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ISVLSI
Authors Shalini Ghosh, Sugato Basu, Nur A. Touba
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