ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper studies some manufacturing test data collected for an experimental digital IC. Test results for a large variety of single-stuck fault based test sets are shown and comp...
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
The use of a single pass/fail threshold for IDDQ testing is unworkable as chip background currents increase to the point where they exceed many defect currents. This paper describ...
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
A tunneling-open failure mode is proposed and carefully studied. A circuit with a tunneling open could pass at-speed Boolean tests but fail VLV testing or IDDQ testing. Theoretica...
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper we present a design for IEEE 1149.1 Test Access Port (TAP)controllers that is based on a practical reuse methodology. While the basic use and core functionality of T...
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for...
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson ...