Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

7

ITC
2000
IEEE

favoriteEmaildiscussreport

53views Hardware» more ITC 2000»

Using on-chip test pattern compression for full scan SoC designs

13 years 9 months ago

Using on-chip test pattern compression for full scan SoC designs

Download www.lirmm.fr

Helmut Lang, Jens Pfeiffer, Jeff Maguire

Real-time Traffic

Hardware | ITC 2000 |

claim paper

Related Content

» Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead

» Efficient SpaceTime Compression to Reduce Test Data Volume and Testing Time for IP Cores

» Onchip ScanBased Test Strategy for a Dependable ManyCore Processor Using a NoC as a Test A...

» Virtual Compression through Test Vector Stitching for Scan Based Designs

» A Technique for High Ratio LZW Compression

» Built in Defect Prognosis for Embedded Memories

Post Info
More Details (n/a)

Added	31 Jul 2010
Updated	31 Jul 2010
Type	Conference
Year	2000
Where	ITC
Authors	Helmut Lang, Jens Pfeiffer, Jeff Maguire

Comments (0)