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ITC
2000
IEEE
80views Hardware» more  ITC 2000»
13 years 9 months ago
A stand-alone integrated test core for time and frequency domain measurements
An area efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstructi...
Mohamed Hafed, Nazmy Abaskharoun, Gordon W. Robert...
ITC
2000
IEEE
76views Hardware» more  ITC 2000»
13 years 9 months ago
Industrial evaluation of DRAM SIMM tests
This paper describes the results of testing 50 single inline memory modules (SIMMs), each containing 16 16Mbit DRAM chips (DUTs); 39 SIMMs failed, and of the 800 DUTs, 116failed. ...
A. J. van de Goor, A. Paalvast
ITC
2000
IEEE
55views Hardware» more  ITC 2000»
13 years 9 months ago
Low power BIST design by hypergraph partitioning: methodology and architectures
Patrick Girard, Christian Landrault, Loïs Gui...
ITC
2000
IEEE
79views Hardware» more  ITC 2000»
13 years 9 months ago
Analysis of failure sources in surface-micromachined MEMS
Nilmoni Deb, Ronald D. Blanton
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
13 years 9 months ago
Reducing test data volume using external/LBIST hybrid test patterns
A common approachfor large industrial designs is to use logic built-in self-test (LBIST)followed by test data from an external tester. Because the fault coverage with LBIST alone ...
Debaleena Das, Nur A. Touba
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
13 years 9 months ago
Deterministic partitioning techniques for fault diagnosis in scan-based BIST
A deterministic partitioning technique for fault diagnosis in Scan-Based BIST is proposed. Properties of high quality partitions for improved fault diagnosis times are identified...
Ismet Bayraktaroglu, Alex Orailoglu