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MICRO
2000
IEEE
121views Hardware» more  MICRO 2000»
13 years 8 months ago
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
Rajeev Balasubramonian, David H. Albonesi, Alper B...
MICRO
2000
IEEE
95views Hardware» more  MICRO 2000»
13 years 8 months ago
Very low power pipelines using significance compression
Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This s...
Ramon Canal, Antonio González, James E. Smi...
MICRO
2000
IEEE
71views Hardware» more  MICRO 2000»
13 years 9 months ago
Improving BTB performance in the presence of DLLs
Dynamically Linked Libraries (DLLs) promote software modularity, portability, and flexibility and their use has become widespread. In this paper, we characterize the behavior of f...
Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tys...
MICRO
2000
IEEE
122views Hardware» more  MICRO 2000»
13 years 9 months ago
Dynamic zero compression for cache energy reduction
Dynamic Zero Compression reduces the energy required for cache accesses by only writing and reading a single bit for every zero-valued byte. This energy-conscious compression is i...
Luis Villa, Michael Zhang, Krste Asanovic
MICRO
2000
IEEE
86views Hardware» more  MICRO 2000»
13 years 9 months ago
On pipelining dynamic instruction scheduling logic
A machine’s performance is the product of its IPC (Instructions Per Cycle) and clock frequency. Recently, Palacharla, Jouppi, and Smith [3] warned that the dynamic instruction s...
Jared Stark, Mary D. Brown, Yale N. Patt
MICRO
2000
IEEE
74views Hardware» more  MICRO 2000»
13 years 9 months ago
Predictor-directed stream buffers
An effective method for reducing the effect of load latency in modern processors is data prefetching. One form of data prefetching, stream buffers, has been shown to be particular...
Timothy Sherwood, Suleyman Sair, Brad Calder
MICRO
2000
IEEE
67views Hardware» more  MICRO 2000»
13 years 9 months ago
Modulo scheduling for a fully-distributed clustered VLIW architecture
F. Jesús Sánchez, Antonio Gonz&aacut...
MICRO
2000
IEEE
124views Hardware» more  MICRO 2000»
13 years 9 months ago
Calpa: a tool for automating selective dynamic compilation
Selective dynamic compilation systems, typically driven by annotations that identify run-time constants, can achieve significant program speedups. However, manually inserting ann...
Markus Mock, Craig Chambers, Susan J. Eggers
MICRO
2000
IEEE
118views Hardware» more  MICRO 2000»
13 years 9 months ago
A study of slipstream processors
A slipstream processor reduces the length of a running program by dynamically skipping computation non-essential for correct forward progress. The shortened program runs faster as...
Zachary Purser, Karthik Sundaramoorthy, Eric Roten...
MICRO
2000
IEEE
98views Hardware» more  MICRO 2000»
13 years 9 months ago
The store-load address table and speculative register promotion
Register promotion is an optimization that allocates a value to a register for a region of its lifetime where it is provably not aliased. Conventional compiler analysis cannot alw...
Matt Postiff, David Greene, Trevor N. Mudge