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ASAP
2008
IEEE
142views Hardware» more  ASAP 2008»
12 years 6 months ago
Managing multi-core soft-error reliability through utility-driven cross domain optimization
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
Wangyuan Zhang, Tao Li
ISCA
2009
IEEE
276views Hardware» more  ISCA 2009»
12 years 6 months ago
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
Many multi-core processors employ a large last-level cache (LLC) shared among the multiple cores. Past research has demonstrated that sharing-oblivious cache management policies (...
Yuejian Xie, Gabriel H. Loh
PPOPP
2009
ACM
13 years 6 days ago
A compiler-directed data prefetching scheme for chip multiprocessors
Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multi...
Dhruva Chakrabarti, Mahmut T. Kandemir, Mustafa Ka...
VLSID
2009
IEEE
139views VLSI» more  VLSID 2009»
13 years 8 days ago
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration
Increasing the number of cores in a multi-core processor reduces per-core performance. On the other hand, providing more resources to each core limits the number of cores on a chi...
Tameesh Suri, Aneesh Aggarwal
DAC
2008
ACM
13 years 20 days ago
Federation: repurposing scalar cores for out-of-order instruction issue
Future SoCs will contain multiple cores. For workloads with significant parallelism, prior work has shown the benefit of many small, multi-threaded, scalar cores. For workloads th...
David Tarjan, Michael Boyer, Kevin Skadron
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