PATMOS
2005
Springer
13 years 10 months ago
2005
Springer
PATMOS
2005
Springer
13 years 10 months ago
2005
Springer
A new method for predicting timing jitter caused by device noise in current-mode logic (CML) frequency dividers is presented. Device noise transformation into jitter is modeled as ...
PATMOS
2005
Springer
13 years 10 months ago
2005
Springer
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...