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HPDC
2010
IEEE
9 years 9 days ago
Towards optimising distributed data streaming graphs using parallel streams
Modern scientific collaborations have opened up the opportunity of solving complex problems that involve multidisciplinary expertise and large-scale computational experiments. The...
Chee Sun Liew, Malcolm P. Atkinson, Jano I. van He...
ERSA
2006
98views Hardware» more  ERSA 2006»
9 years 18 days ago
Hydra: An Energy-efficient and Reconfigurable Network Interface
Abstract-- In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is us...
Marcel D. van de Burgwal, Gerard J. M. Smit, Gerar...
CVPR
1996
IEEE
9 years 3 months ago
Connectionist networks for feature indexing and object recognition
Feature indexing techniques are promising for object recognition since they can quickly reduce the set of possible matches for a set of image features. This work exploits another ...
Clark F. Olson
HIPC
2003
Springer
9 years 4 months ago
Performance Analysis of Blue Gene/L Using Parallel Discrete Event Simulation
High performance computers currently under construction, such as IBM’s Blue Gene/L, consisting of large numbers (64K) of low cost processing elements with relatively small local...
Ed Upchurch, Paul L. Springer, Maciej Brodowicz, S...
CODES
2003
IEEE
9 years 4 months ago
Programmers' views of SoCs
System-on-chip (SoC) designs have the potential to change the way we organize computation. This potential has gone unrealized. Future SoCs will have multiple heterogeneous process...
JoAnn M. Paul
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
9 years 4 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
IPPS
2006
IEEE
9 years 5 months ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...
FCCM
2006
IEEE
268views VLSI» more  FCCM 2006»
9 years 5 months ago
Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs
We present an architecture and an implementation of an FPGA-based sparse matrix-vector multiplier (SMVM) for use in the iterative solution of large, sparse systems of equations ar...
Yousef El-Kurdi, Warren J. Gross, Dennis Giannacop...
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