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RSP
2005
IEEE
11 years 11 months ago
Rapid Development Methodology for Customized Middleware
Thomas Vergnaud, Jérôme Hugues, Laure...
RSP
2005
IEEE
11 years 11 months ago
Prototyping a Residential Gateway Using Xilinx ISE
This paper presents a residential gateway (RG) prototyping process using Xilinx Integrated Software Environment (ISE) version 6.1i. The RG was designed for broadband residential m...
S. W. Song, J. D. Zheng, William B. Gardner
RSP
2005
IEEE
131views Control Systems» more  RSP 2005»
11 years 11 months ago
Models for Embedded Application Mapping onto NoCs: Timing Analysis
Networks-on-chip (NoCs) are an emergent communication infrastructure, which can be designed to deal with growing system complexity and technology evolution. The efficient use of N...
César A. M. Marcon, Márcio Eduardo K...
RSP
2005
IEEE
155views Control Systems» more  RSP 2005»
11 years 11 months ago
Optimization Techniques for ADL-Driven RTL Processor Synthesis
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Ma...
RSP
2005
IEEE
162views Control Systems» more  RSP 2005»
11 years 11 months ago
SyCE: An Integrated Environment for System Design in SystemC
We present an integrated system design environment for SystemC, called SyCE. The system consists of several components for efficient analysis, verification and debugging of Syst...
Rolf Drechsler, Görschwin Fey, Christian Genz...
RSP
2005
IEEE
207views Control Systems» more  RSP 2005»
11 years 11 months ago
Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design
Embedded signal processing systems are usually associated with real-time constraints and/or high data rates so that fully software implementation are often not satisfactory. In th...
Sylvain Huet, Emmanuel Casseau, Olivier Pasquier
RSP
2005
IEEE
107views Control Systems» more  RSP 2005»
11 years 11 months ago
Rapid Prototyping of Embedded Software Using Selective Formalism
Our software synthesis tool, CSP++, generates C++ source code from verifiable CSPm specifications, and includes a framework for runtime execution. Our technique of selective for...
John D. Carter, Ming Xu, William B. Gardner
RSP
2005
IEEE
108views Control Systems» more  RSP 2005»
11 years 11 months ago
Enabling a Real-Time Solution for Neuron Detection with Reconfigurable Hardware
Ben Cordes, Jennifer G. Dy, Miriam Leeser, James G...
RSP
2005
IEEE
164views Control Systems» more  RSP 2005»
11 years 11 months ago
High Level Synthesis for Data-Driven Applications
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley,...
RSP
2005
IEEE
11 years 11 months ago
Test-Time, Run-Time, and Simulation-Time Temporal Assertions in RSP
For cost-effective prototyping, system designers should have a clear understanding of the intended use of the prototype under development. This paper describes a classification of...
Doron Drusinsky, Man-tak Shing, Kadir Alpaslan Dem...
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