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VTS
2005
IEEE

116views Hardware» more VTS 2005»

Closed-Form Simulation and Robustness Models for SEU-Tolerant Design

12 years 11 months ago

— A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SP...

Kartik Mohanram

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VTS
2006
IEEE

101views Hardware» more VTS 2006»

Design Optimization for Robustness to Single Event Upsets

13 years 1 days ago

Download www.ece.rice.edu

Abstract: An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU...

Quming Zhou, Mihir R. Choudhury, Kartik Mohanram

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ICCAD
2006
IEEE

141views Hardware» more ICCAD 2006»

Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques

13 years 2 months ago

Download www.ece.rice.edu

An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustne...

Mihir R. Choudhury, Quming Zhou, Kartik Mohanram

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DAC
2006
ACM

84views Computer Architecture» more DAC 2006»

A family of cells to reduce the soft-error-rate in ternary-CAM

13 years 7 months ago

Download www.eecg.toronto.edu

Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These eve...

Navid Azizi, Farid N. Najm

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