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2006
IEEE

Design Optimization for Robustness to Single Event Upsets

12 years 8 months ago
Design Optimization for Robustness to Single Event Upsets
Abstract: An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model is integrated with area and performance constraints into an optimization framework based on geometric programming for design space exploration. Simulation results demonstrate the design tradeoffs that can be achieved with this approach.
Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
Added 12 Jun 2010
Updated 12 Jun 2010
Type Conference
Year 2006
Where VTS
Authors Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
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