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13

VTS
2005
IEEE

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Closed-Form Simulation and Robustness Models for SEU-Tolerant Design

13 years 10 months ago

Closed-Form Simulation and Robustness Models for SEU-Tolerant Design

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— A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SPICEbased calibration of logic gates for a range of values of fanout, charge, and scale factor is presented. A full set of experimental results demonstrate that on average, the model is accurate to within 5% of the results obtained using SPICE with over 100X improvement in computational speed. Besides simulation and analysis of SEU-induced transients, the proposed model can be used to perform reliability-aware logic synthesis through the incorporation of robustness metrics to tune cell libraries.

Kartik Mohanram

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Linear Rc Model | Single-event Upsets | Voltage Transients | VTS 2005 |

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Added	25 Jun 2010
Updated	25 Jun 2010
Type	Conference
Year	2005
Where	VTS
Authors	Kartik Mohanram

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