ICCAD
1996
IEEE
13 years 9 months ago
1996
IEEE
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
Partially depleted silicon-on-insulator (PD-SOI) has emerged as a technology of choice for high-performance low-power deep-submicrometer digital integrated circuits. An important c...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will...
CEC
2005
IEEE
13 years 10 months ago
2005
IEEE
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—We investigate restructuring techniques based on decomposition/factorization, with the objective to move critical signals toward the output while minimizing area. A specific ap...