FPGA
1998
ACM
13 years 8 months ago
1998
ACM
In this paper, we present a new retiming-based technology mapping algorithm for look-up table-based eld programmable gate arrays. The algorithm is based on a novel iterative proce...
ISPD
2004
ACM
13 years 10 months ago
2004
ACM
Due to increasing design complexity, routing congestion has become a critical problem in VLSI designs. This paper introduces a distributed metric to predict routing congestion for...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
DAC
2000
ACM
14 years 5 months ago
2000
ACM
In this paper, we study the incremental t echnology mapping problem for lookup-table (LUT) based Field Programmable Gate Arrays (FPGAs) under incremental changes. Given a gate-lev...