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FDTC
2010
Springer
118views Cryptology» more  FDTC 2010»
9 years 18 days ago
Low Cost Built in Self Test for Public Key Crypto Cores
The testability of the cryptographic cores brings in an extra dimension to the process of digital circuits testing
Dusko Karaklajic, Miroslav Knezevic, Ingrid Verbau...
TC
2008
9 years 2 months ago
Low-Transition Test Pattern Generation for BIST-Based Applications
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during te...
Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed
DFT
2004
IEEE
95views VLSI» more  DFT 2004»
9 years 6 months ago
Mixed Loopback BiST for RF Digital Transceivers
In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generat...
Jerzy Dabrowski, Javier Gonzalez Bayon
ITC
1992
IEEE
76views Hardware» more  ITC 1992»
9 years 6 months ago
A Small Test Generator for Large Designs
In this paper we report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. t...
Sandip Kundu, Leendert M. Huisman, Indira Nair, Vi...
ICCAD
1997
IEEE
147views Hardware» more  ICCAD 1997»
9 years 6 months ago
Built-in test generation for synchronous sequential circuits
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
Irith Pomeranz, Sudhakar M. Reddy
ITC
1998
IEEE
114views Hardware» more  ITC 1998»
9 years 6 months ago
BETSY: synthesizing circuits for a specified BIST environment
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
Zhe Zhao, Bahram Pouya, Nur A. Touba
ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
9 years 6 months ago
Test pattern generation for width compression in BIST
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
Paulo F. Flores, Horácio C. Neto, K. Chakra...
DATE
2000
IEEE
130views Hardware» more  DATE 2000»
9 years 7 months ago
Optimal Hardware Pattern Generation for Functional BIST
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, H...
IOLTS
2005
IEEE
206views Hardware» more  IOLTS 2005»
9 years 8 months ago
A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage
This paper proposes a new test pattern generator (TPG) which is an enhancement of GLFSR (Galois LFSR). This design is based on certain non–binary error detecting codes, formulat...
Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir
DFT
2006
IEEE
125views VLSI» more  DFT 2006»
9 years 8 months ago
Synthesis of Efficient Linear Test Pattern Generators
This paper presents a procedure for Synthesis of LINear test pattern Generators called SLING. SLING can synthesize linear test pattern generators that satisfy constraints on area,...
Avijit Dutta, Nur A. Touba
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