Sciweavers

DATE
2003
IEEE
114views Hardware» more  DATE 2003»
13 years 10 months ago
A New Approach to Test Generation and Test Compaction for Scan Circuits
We propose a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors...
Irith Pomeranz, Sudhakar M. Reddy
DSD
2005
IEEE
106views Hardware» more  DSD 2005»
13 years 10 months ago
Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
DFT
2006
IEEE
105views VLSI» more  DFT 2006»
13 years 11 months ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...
HASE
2008
IEEE
13 years 11 months ago
An Interaction-Based Test Sequence Generation Approach for Testing Web Applications
Web applications often use dynamic pages that interact with each other by accessing shared objects, e.g., session objects. Interactions between dynamic pages need to be carefully ...
Wenhua Wang, Sreedevi Sampath, Yu Lei, Raghu Kacke...