ASPDAC
1995
ACM
13 years 8 months ago
1995
ACM
Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on tes...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
DSD
2008
IEEE
13 years 11 months ago
2008
IEEE
Testability is one of the most important factors that are considered during design cycle along with reliability, speed, power consumption, cost and other factors important for a c...