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ASPDAC
1995
ACM
130views Hardware» more  ASPDAC 1995»
9 years 2 months ago
Design for testability using register-transfer level partial scan selection
Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on tes...
Akira Motohara, Sadami Takeoka, Toshinori Hosokawa...
EURODAC
1994
IEEE
145views VHDL» more  EURODAC 1994»
9 years 3 months ago
Testability analysis and improvement from VHDL behavioral specifications
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
DSD
2008
IEEE
85views Hardware» more  DSD 2008»
9 years 5 months ago
TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path
Testability is one of the most important factors that are considered during design cycle along with reliability, speed, power consumption, cost and other factors important for a c...
Josef Strnadel
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