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ASPDAC
1995
ACM

Design for testability using register-transfer level partial scan selection

10 years 3 months ago
Design for testability using register-transfer level partial scan selection
Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on testability analysis for RTL design including data path circuits and control circuits such as state machines. Registers and state machines which make gate level ATPG difficult are identified by the scan selection technique based on RTL testability analysis effectively. Experimental results for actual circuits are also presented.
Akira Motohara, Sadami Takeoka, Toshinori Hosokawa
Added 25 Aug 2010
Updated 25 Aug 2010
Type Conference
Year 1995
Where ASPDAC
Authors Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka
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