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ISCAS
2011
IEEE
288views Hardware» more  ISCAS 2011»
10 years 9 months ago
Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes
—We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered de...
Yang Sun, Guohui Wang, Joseph R. Cavallaro
TVLSI
2010
10 years 12 months ago
Design and Implementation of a Sort-Free K-Best Sphere Decoder
:- This paper describes the design and VLSI architecture for a 4x4 breadth first K-Best MIMO decoder using a 64 QAM scheme. A novel sort free approach to path extension, as well as...
Sudip Mondal, Ahmed M. Eltawil, Chung-An Shen, Kha...
VLSISP
2002
93views more  VLSISP 2002»
11 years 4 months ago
Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers
Abstract. This paper presents a reduced-complexity, fixed-point algorithm and efficient real-time VLSI architectures for multiuser channel estimation, one of the core baseband proc...
Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. ...
ISQED
2009
IEEE
328views Hardware» more  ISQED 2009»
12 years 1 days ago
VLSI architectures of perceptual based video watermarking for real-time copyright protection
For effective digital rights management (DRM) of multimedia in the framework of embedded systems, both watermarking and cryptography are necessary. In this paper, we present a wat...
Saraju P. Mohanty, Elias Kougianos, Wei Cai, Manis...
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