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FCCM
2004
IEEE
118views VLSI» more  FCCM 2004»
9 years 11 months ago
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor
Reconfigurable System-on-Chip (SoC) platforms that incorporate hard-core processors surrounded by large amounts of FPGA are today commodities: the reconfigurable logic is often us...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
FCCM
2004
IEEE
95views VLSI» more  FCCM 2004»
9 years 11 months ago
An Arithmetic Library and Its Application to the N-body Problem
Kuen Hung Tsoi, Chun Hok Ho, H. C. Yeung, Philip H...
FCCM
2004
IEEE
121views VLSI» more  FCCM 2004»
9 years 11 months ago
Validation of an Advanced Encryption Standard (AES) IP Core
This paper describes the package of test bench code required to verify the Algotronix' AES IP Core. Several authors (see the references in [3]) have published papers detailing...
Valeri F. Tomashau, Tom Kean
FCCM
2004
IEEE
90views VLSI» more  FCCM 2004»
9 years 11 months ago
Migrating Functionality from ROMS to Embedded Multipliers
This poster proposes a technique, based on polynomial approximation, which can be applied to convert ROMs into a combination of arithmetic operations and smaller ROMs. We show tha...
Gareth W. Morris, George A. Constantinides, Peter ...
FCCM
2004
IEEE
103views VLSI» more  FCCM 2004»
9 years 11 months ago
A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder
The development of turbo codes has allowed for nearShannon limit information transfer in modern communication systems. Although turbo decoding is viewed as superior to alternate d...
Jian Liang, Russell Tessier, Dennis Goeckel
FCCM
2004
IEEE
102views VLSI» more  FCCM 2004»
9 years 11 months ago
Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications
We demonstrate the use of a "smart camera" to accelerate two very different image processing applications. The smart camera consists of a high quality video camera and f...
Miriam Leeser, Shawn Miller, Haiqian Yu
FCCM
2004
IEEE
175views VLSI» more  FCCM 2004»
9 years 11 months ago
A Flexible Hardware Encoder for Low-Density Parity-Check Codes
We describe a flexible hardware encoder for regular and irregular low-density parity-check (LDPC) codes. Although LDPC codes achieve achieve better performance and lower decoding ...
Dong-U Lee, Wayne Luk, Connie Wang, Christopher Jo...
FCCM
2004
IEEE
101views VLSI» more  FCCM 2004»
9 years 11 months ago
Hardware-in-the-Loop Evolution of a 3-bit Multiplier
Gregory V. Larchev, Jason D. Lohn
FCCM
2004
IEEE
130views VLSI» more  FCCM 2004»
9 years 11 months ago
Hyperreconfigurable Architectures for Fast Run Time Reconfiguration
Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit changing needs of a computation during run time. The increasing...
Sebastian Lange, Martin Middendorf
FCCM
2004
IEEE
136views VLSI» more  FCCM 2004»
9 years 11 months ago
The MOLEN Processor Prototype
We present a prototype design of the MOLEN polymorphic processor, a CCM based on the co-processor architectural paradigm. The Xilinx Virtex II Pro technology is used as a prototyp...
Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassi...
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