Sciweavers

Share
VTS
2000
IEEE
137views Hardware» more  VTS 2000»
9 years 2 months ago
Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method
This paper proposes a new method based on analytic signal theory for extracting both instantaneous and RMS sinusoidal jitter from PLL output signals. The method relies on the exte...
Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma,...
VTS
2000
IEEE
108views Hardware» more  VTS 2000»
9 years 2 months ago
Cold Delay Defect Screening
Delay defects can escape detection during the normal production test flow, particularly if they do not affect any of the long paths included in the test flow. Some defect types ca...
Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao...
VTS
2000
IEEE
126views Hardware» more  VTS 2000»
9 years 2 months ago
Static Compaction Techniques to Control Scan Vector Power Dissipation
Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause prob...
Ranganathan Sankaralingam, Rama Rao Oruganti, Nur ...
VTS
2000
IEEE
89views Hardware» more  VTS 2000»
9 years 2 months ago
Fault Escapes in Duplex Systems
Hardware duplication techniques are widely used for concurrent error detection in dependable systems to ensure high availability and data integrity. These techniques are vulnerabl...
Subhasish Mitra, Nirmal R. Saxena, Edward J. McClu...
VTS
2000
IEEE
95views Hardware» more  VTS 2000»
9 years 2 months ago
Word Voter: A New Voter Design for Triple Modular Redundant Systems
Redundancy techniques are commonly used to design dependable systems to ensure high reliability, availability and data integrity. Triple Modular Redundancy (TMR) is a widely used ...
Subhasish Mitra, Edward J. McCluskey
VTS
2000
IEEE
76views Hardware» more  VTS 2000»
9 years 2 months ago
Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems
Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the e arly stages.We outline a methodolo gy and toolset to ena...
Sule Ozev, Alex Orailoglu
VTS
2000
IEEE
103views Hardware» more  VTS 2000»
9 years 2 months ago
Invariance-Based On-Line Test for RTL Controller-Datapath Circuits
We present a low-cost on-line test methodology for RTL controller-datapath pairs, based on the notion of path invariance. The fundamental observation supporting the proposed metho...
Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailogl...
VTS
2000
IEEE
167views Hardware» more  VTS 2000»
9 years 2 months ago
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukher...
VTS
2000
IEEE
99views Hardware» more  VTS 2000»
9 years 2 months ago
Virtual Scan Chains: A Means for Reducing Scan Length in Cores
A novel design-for-test (DFT) technique is presented for designing a core with a “virtual scan chain” which looks (to the system integrator) like it is shorter than the real s...
Abhijit Jas, Bahram Pouya, Nur A. Touba
books