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ISCA
1991
IEEE
110views Hardware» more  ISCA 1991»
15 years 8 months ago
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width
When address reference streams exhibit high degrees of spatial and temporal locality, many of the higher order address lines carry redundant information. By caching the higher ord...
Matthew K. Farrens, Arvin Park
ISCA
1991
IEEE
162views Hardware» more  ISCA 1991»
15 years 8 months ago
Comparison of Hardware and Software Cache Coherence Schemes
We use mean value analysis models to compare representative hardware and software cache coherence schemes for a large-scale shared-memory system. Our goal is to identify the workl...
Sarita V. Adve, Vikram S. Adve, Mark D. Hill, Mary...
IFIP
1992
Springer
15 years 8 months ago
Human Factors In Computer Security
Ibibia Dabipi, Husam Yaghi, Issam Qasem
92
Voted
IPPS
1991
IEEE
15 years 8 months ago
An Algorithm for Generating Node Disjoint Routes in Kautz Digraphs
Gerard J. M. Smit, Paul J. M. Havinga, Pierre G. J...