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125
Voted
MICRO
1995
IEEE
102views Hardware» more  MICRO 1995»
15 years 8 months ago
Zero-cycle loads: microarchitecture support for reducing load latency
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
Todd M. Austin, Gurindar S. Sohi
216
Voted
VL
1997
IEEE
295views Visual Languages» more  VL 1997»
15 years 8 months ago
Semantics of Visual Languages
Martin Erwig
MICRO
1995
IEEE
85views Hardware» more  MICRO 1995»
15 years 8 months ago
The predictability of branches in libraries
Brad Calder, Dirk Grunwald, Amitabh Srivastava
146
Voted
MICRO
1995
IEEE
140views Hardware» more  MICRO 1995»
15 years 8 months ago
A system level perspective on branch architecture performance
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...
Brad Calder, Dirk Grunwald, Joel S. Emer
MICRO
1995
IEEE
72views Hardware» more  MICRO 1995»
15 years 8 months ago
Dynamic rescheduling: a technique for object code compatibility in VLIW architectures
Lack of object code compatibility in VLIW architectures is a severe limit to their adoption as a generalpurpose computing paradigm. Previous approaches include hardware and softwa...
Thomas M. Conte, Sumedh W. Sathaye