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ASAP
2006
IEEE
131views Hardware» more  ASAP 2006»
15 years 7 months ago
A Generic Multi-Phase On-Chip Traffic Generation Environment
We present hereafter a framework for on-chip traffic generation and networks-on-chip performance evaluation. This framework is based on a traffic generator that has three importan...
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset
ASAP
2006
IEEE
114views Hardware» more  ASAP 2006»
15 years 7 months ago
The Mythical CCM: In Search of Usable (and Resuable) FPGA-Based General Computing Machines
Early FPGA researchers understood that FPGAs made possible the creation of a new, flexible, and powerful class of machine -- the configurable computing machine (CCM). The earliest...
Brent E. Nelson
ASAP
2006
IEEE
138views Hardware» more  ASAP 2006»
15 years 7 months ago
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
Marjan Karkooti, Predrag Radosavljevic, Joseph R. ...
ASAP
2006
IEEE
108views Hardware» more  ASAP 2006»
15 years 7 months ago
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding
State-of-the-art communication standards make extensive use of Turbo codes. The complex and power consuming designs that currently implement the turbo decoder expose the need for ...
Pablo Ituero, Marisa López-Vallejo
ASAP
2006
IEEE
168views Hardware» more  ASAP 2006»
15 years 7 months ago
Dual-Processor Design of Energy Efficient Fault-Tolerant System
A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the completion of the prim...
Shaoxiong Hua, Pushkin R. Pari, Gang Qu