— A new methodology for SoC-level logic-IP-internal EM verification is presented, which provides an on-the-fly retargeting capability for reliability constraints. This flexibilit...
Palkesh Jain, Sachin S. Sapatnekar, Jordi Cortadel...
—In advanced technology node, not only process variations but also aging effects have critical impacts on circuit performance. Most of existing works consider process variations ...
Yen-Lung Chen, Wei Wu, Chien-Nan Jimmy Liu, Lei He
—Energy becomes the primary concern in nowadays multi-core architecture designs. Moore’s law predicts that the exponentially increasing number of cores can be packed into a sin...
Qiaosha Zou, Matthew Poremba, Rui He, Wei Yang, Ju...
Probing attack is a severe threat for the security of hardware cryptographic modules (HCMs). In this paper, we make the first step to evaluate the vulnerability of HCMs against p...
Lingxiao Wei, Jie Zhang, Feng Yuan, Yannan Liu, Ju...
—As the feature size keeps scaling down and the circuit complexity increases rapidly, a more advanced hybrid lithography, which combines multiple patterning and e-beam lithograph...
Yunfeng Yang, Wai-Shing Luk, Hai Zhou, Changhao Ya...