196
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DAC
2005
ACM
16 years 8 months ago
2005
ACM
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
187
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DAC
2005
ACM
16 years 8 months ago
2005
ACM
An efficient approach to full-wave impedance extraction is developed that accounts for substrate effects through the use of two-layer media Green's functions in a mixed-poten...
209
click to vote
DAC
2005
ACM
16 years 8 months ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
167
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DAC
2005
ACM
16 years 8 months ago
2005
ACM
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...
162
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DAC
2005
ACM
16 years 8 months ago
2005
ACM
While the past research discussed several advantages of multiprocessor-system-on-a-chip (MPSOC) architectures from both area utilization and design verification perspectives over ...