213
Voted
DAC
2002
ACM
16 years 8 months ago
2002
ACM
The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction i...
158
Voted
DAC
2002
ACM
16 years 8 months ago
2002
ACM
182
click to vote
DAC
2002
ACM
16 years 8 months ago
2002
ACM
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool ...
185
click to vote
DAC
2002
ACM
16 years 8 months ago
2002
ACM
This paper presents efficient automatic code synthesis techniques from dataflow graphs for multimedia applications. Since multimedia applications require large size buffers contai...
180
Voted
DAC
2002
ACM
16 years 8 months ago
2002
ACM
Conventional global routing minimizes total wire length and congestion. Experiments using large industrial benchmark circuits show that up to 24% of nets in such routing solutions...