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TVLSI
2016
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10 years 12 days ago
Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs
—Triple patterning lithography (TPL) is regarded as a promising technique to handle the manufacturing challenges in the 14nm technology node and beyond. It is necessary to consid...
Jian Kuang 0001, Wing-Kai Chow, Evangeline F. Y. Y...
TVLSI
2016
69views more  TVLSI 2016»
10 years 12 days ago
Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing
Abstract—A field-assisted spin-torque transfer magnetoresistive RAM (STT-MRAM) cache is presented for the use in high-performance energy-efficient microprocessors. Adding fiel...
Ravi Patel, Xiaochen Guo, Qing Guo, Engin Ipek, Eb...
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TVLSI
2016
56views more  TVLSI 2016»
10 years 12 days ago
NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices
—In recent years, the demand for NAND flash-based storage devices has rapidly increased because of the popularization of various portable devices. NAND flash memory (NFM) offer...
Jinyoung Kim, Sang-Hoon Park, Hyeokjun Seo, Ki-Wha...
TVLSI
2016
52views more  TVLSI 2016»
10 years 12 days ago
Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization
—Ultralow-power subthreshold logic circuits are becoming prominent in embedded applications with limited energy budgets. Minimum energy consumption of digital logic circuits can ...
Mahmoud Zangeneh, Ajay Joshi
TVLSI
2016
56views more  TVLSI 2016»
10 years 12 days ago
Improve Chip Pin Performance Using Optical Interconnects
—With the fast development of processor chips, power-efficient, high-bandwidth, and low-latency interchip interconnects become more and more important. Studies show that the ban...
Zhehui Wang, Jiang Xu, Peng Yang, Xuan Wang, Zhe W...