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DATE
2000
IEEE

A 50 Mbit/s Iterative Turbo-Decoder

14 years 2 months ago
A 50 Mbit/s Iterative Turbo-Decoder
Very low bit error rate has become an important constraint in high performance communication systems that operate at very low signal to noise ratios: due to their impressive coding gains, turbo codes have been proposed for several applications, although they suffer a large decoding delay. This paper presents the design of a turbo decoder with high performances in terms of throughput implemented using TSPC (True Single Phase Clocking) logic family. In order to achieve the best compromise between cost (in terms of area) and throughput, several architectural solutions have been analyzed. The whole system and in particular its core, the SISO module, has been verified through VHDL simulations. HSPICE simulations show that the system can operate with a 1 GHz clock and thus it can reach a throughput of 50 Mbit/s.
F. Viglione, Guido Masera, Gianluca Piccinini, Mas
Added 30 Jul 2010
Updated 30 Jul 2010
Type Conference
Year 2000
Where DATE
Authors F. Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
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