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ISPASS
2005
IEEE

Accelerating Multiprocessor Simulation with a Memory Timestamp Record

13 years 9 months ago
Accelerating Multiprocessor Simulation with a Memory Timestamp Record
We introduce a fast and accurate technique for initializing the directory and cache state of a multiprocessor system based on a novel software structure called the memory timestamp record (MTR). The MTR is a versatile, compressed snapshot of memory reference patterns which can be rapidly updated during fast-forwarded simulation, or stored as part of a checkpoint. We evaluate MTR using a full-system simulation of a directory-based cachecoherent multiprocessor running a range of multithreaded workloads. Both MTR and a multiprocessor version of functional fast-forwarding (FFW) make similar performance estimates, usually within 15% of our detailed model. In addi
Kenneth C. Barr, Heidi Pan, Michael Zhang, Krste A
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where ISPASS
Authors Kenneth C. Barr, Heidi Pan, Michael Zhang, Krste Asanovic
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