On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping

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On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping
In this paper we study the area and depth trade-off in LUT based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a number of depth relaxation operations to obtain a new network with bounded increase in depth and advantageous to subsequent re-mapping for area minimization. We then re-map the resulting network to obtain an area-minimized mapping solution. By gradually increasing the depth bound, for each design we are able to produce a set of mapping solutions with smooth area and depth trade-off. For the area minimization step, we have developed an optimal algorithm for computing an area-minimum mapping solution without node duplication. Experimental results show that our solution sets outperform the solutions produced by many existing mapping algorithms in terms of both area and depth minimization.
Jason Cong, Yuzheng Ding
Added 09 Aug 2010
Updated 09 Aug 2010
Type Conference
Year 1993
Where DAC
Authors Jason Cong, Yuzheng Ding
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