An Automatic Router for the Pin Grid Array Package

A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to-pin nets on one or more layers. This router consists of three phases: layer assignment, topological routing, and geometrical routing. Examples tested on a windowsbased environment show that our router is efficient and can complete the routing task with less substrate layers. Compared to the manual routing, this router owns a friendly graphic user interface and can be practically applied to VLSI packaging.

• Type: Conference
• Year: 1999
• Where: ASPDAC
• Authors: Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai
• Keywords: ASPDAC 1999, Hardware, Package Router, Router, Topological Routing