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RTAS
2006
IEEE

Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks

13 years 8 months ago
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timing predictability of single real-time tasks has been the focus of much research, bounding the overhead of cache warm-ups after preemptions remains a challenging problem, particularly for data caches. In this paper, we bound the penalty of cache interference for real-time tasks by providing accurate predictions of the data cache behavior across preemptions. For every task, we derive data cache reference patterns for all scalar and non-scalar references. Partial timing of a task is performed up to a preemption point using these patterns. The effects of cache interference are then analyzed using a settheoretic approach, which identifies the number and location of additional misses due to preemption. A feedback mechanism provides the means to interact with the timing analyzer, which subsequently times another in...
Harini Ramaprasad, Frank Mueller
Added 12 Jun 2010
Updated 12 Jun 2010
Type Conference
Year 2006
Where RTAS
Authors Harini Ramaprasad, Frank Mueller
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