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DDECS
2006
IEEE

A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming

13 years 9 months ago
A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming
Abstract-- Genetic Parallel Programming (GPP) evolves parallel programs for MIMD architectures with multiple arithmetic/logic processors (MAPs). This paper describes a tool intended for rapid development of GPP applications. A new software tool is proposed which is able to generate a simulator (in C language) of the MAP and a VHDL implementation of the MAP whose structure and parameters are specified in an input xml file. The proposed tool is intended to serve as first version of the core generator for MAPs utilized in GPP. Typical MAPs are synthetized and their performance is compared against the simulation running on a common PC for a typical task
Zbysek Gajda
Added 22 Aug 2010
Updated 22 Aug 2010
Type Conference
Year 2006
Where DDECS
Authors Zbysek Gajda
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