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51

GLVLSI
1998
IEEE

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A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits

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A Design-for-Testability Technique for Detecting Delay Faults in Logic Circuits

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Kaamran Raahemifar, Majid Ahmadi

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GLVLSI 1998 | VLSI |

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Added	04 Aug 2010
Updated	04 Aug 2010
Type	Conference
Year	1998
Where	GLVLSI
Authors	Kaamran Raahemifar, Majid Ahmadi

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