Design for Verification of the PCI-X Bus

13 years 9 months ago
Design for Verification of the PCI-X Bus
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In this paper, we provide a design for verification approach of a PCI-X bus model, which is the fastest and latest extension of PCI technologies. We use two different modeling levels, namely UML and AsmL. We integrate the verification within the design phases where we use model checking and model based testing, respectively at the AsmL and SystemC levels. This case study presents an illustration of the integration of formal methods and simulations for the purpose of providing better verification results of SystemC IPs. I. MOTIVATION AND PROPOSED METHODOLOGY With the advent of high technology applications, an increasingly evident need has been that of incorporating the traditional microprocessor, memories and peripherals on a single silicon. This is what has marked the beginning of the Systemon-Chip (SoC) era. An S...
Haja Moinudeen, Ali Habibi, Sofiène Tahar
Added 22 Aug 2010
Updated 22 Aug 2010
Type Conference
Year 2006
Authors Haja Moinudeen, Ali Habibi, Sofiène Tahar
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